The present invention relates to a data processing system consisting of a main memory, a central processing unit (CPU), an I/O processor and other structure known to those of skill in the art, and, more particularly, to an address control system for accessing the main memory during data transfer between the main memory and the I/O processor.
In a conventional data processing system, input/output operation between the main memory and the I/O processor is controlled by the I/O processor after control data required for data transfer are transferred to the I/O processor from the CPU. For example, the control data for data transfer are stored in a region of the main memory in the form of a channel control block (CCB) by the CPU. The start address of that region, i.e., the start address of the channel control block, is transferred to a channel, or the like, of the I/O processor. The channel reads out the channel control block from the main memory in accordance with the start address. The channel accesses the main memory in accordance with a data transfer start address stored in a predetermined address of the channel control block so that the data transfer begins.
A data processing system such as described above is disadvantageous, since it is strongly dependent on the architecture of the CPU, e.g., a channel is closely related to the CPU. For this reason, when the architecture of the CPU is changed and the bit length of the address becomes longer, the channel can no longer be used.
If a system with an address having a long bit length, that is, a virtual storage system, is to be implemented, there is an increase in both the number of signal lines for address buses in the I/O buses and the number of driver/receiver gates to be connected to such signal lines, according to the bit length.
This drawback is due to the fact that the I/O processor produces the address data for accessing the main memory.